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<H1>SHLD -- Double Precision Shift Left</H1>

<PRE>
Opcode   Instruction          Clocks   Description

0F  A4   SHLD r/m16,r16,imm8  3/7      r/m16 gets SHL of r/m16 concatenated
                                       with r16
0F  A4   SHLD r/m32,r32,imm8  3/7      r/m32 gets SHL of r/m32 concatenated
                                       with r32
0F  A5   SHLD r/m16,r16,CL    3/7      r/m16 gets SHL of r/m16 concatenated
                                       with r16
0F  A5   SHLD r/m32,r32,CL    3/7      r/m32 gets SHL of r/m32 concatenated
                                       with r32
</PRE>


<H2>Operation</H2>

<PRE>
(* count is an unsigned integer corresponding to the last operand of the
instruction, either an immediate byte or the byte in register CL *)
ShiftAmt := count MOD 32;
inBits := register; (* Allow overlapped operands *)
IF ShiftAmt = 0
THEN no operation
ELSE
   IF ShiftAmt >= OperandSize
   THEN (* Bad parameters *)
      r/m := UNDEFINED;
      CF, OF, SF, ZF, AF, PF := UNDEFINED;
   ELSE (* Perform the shift *)
      CF := BIT[Base, OperandSize - ShiftAmt];
         (* Last bit shifted out on exit *)
   FOR i := OperandSize - 1 DOWNTO ShiftAmt
   DO
      BIT[Base, i] := BIT[Base, i - ShiftAmt];
   OF;
   FOR i := ShiftAmt - 1 DOWNTO 0
   DO
      BIT[Base, i] := BIT[inBits, i - ShiftAmt + OperandSize];
   OD;
   Set SF, ZF, PF (r/m);
      (* SF, ZF, PF are set according to the value of the result *)
   AF := UNDEFINED;
   FI;
FI;
</PRE>

<H2>Description</H2>

SHLD shifts the first operand provided by the r/m field to the left as
many bits as specified by the count operand. The second operand (r16 or r32)
provides the bits to shift in from the right (starting with bit 0). The
result is stored back into the r/m operand. The register remains unaltered.
<P>
The count operand is provided by either an immediate byte or the contents
of the CL register. These operands are taken MODULO 32 to provide a number
between 0 and 31 by which to shift. Because the bits to shift are provided
by the specified registers, the operation is useful for multiprecision
shifts (64 bits or more). The SF, ZF and PF flags are set according to the
value of the result. CF is set to the value of the last bit shifted out. OF
and AF are left undefined.

<H2>Flags Affected</H2>

SF, ZF, PF, and CF as described above; AF and OF are undefined

<H2>Protected Mode Exceptions</H2>

#GP(0) if the result is in a nonwritable segment; #GP(0) for an illegal
memory operand effective address in the CS, DS, ES, FS, or GS segments;
#SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page
fault

<H2>Real Address Mode Exceptions</H2>

Interrupt 13 if any part of the operand would lie outside of the effective
address space from 0 to 0FFFFH

<H2>Virtual 8086 Mode Exceptions</H2>

Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault


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<B>up:</B> <A HREF="c17.htm">
Chapter 17 -- 80386 Instruction Set</A><BR>
<B>prev:</B><A HREF="SGDT.htm"> SGDT/SIDT Store Global/Interrupt Descriptor Table Register</A><BR>
<B>next:</B><A HREF="SHRD.htm"> SHRD Double Precision Shift Right</A>
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